The present invention relates to a data transfer system, a data transfer management apparatus and a data transfer method, and more particularly to a data transfer system capable of making more effective use of the transfer band of data.
The IEEE 1394 high performance serial bus standards (hereinafter referred to as the IEEE 1394 standards) have been developed as the bus standards for transferring multi-media data in real time and at high rate.
In the IEEE 1394 standards, three data transfer modes, called S100 (98.304 Mbps), S200 (196.608 Mbps) and S400 (393.216 Mbps), are defined, a 1394 port having an upper transfer rate being provided to keep inconsistency with its lower transfer rate. Thereby, the data transfer rates of S100, S200 and S400 can be mixed on the same network. In the IEEE standards, a so-called DS-Link (Data/Strobe Link) encoding method is employed as the transfer format.
In the DS-Link encoding method, the transfer data is transformed into a data signal and a strobe signal for supplementing the data signal, in which a clock can be generated by taking an exclusive-OR of these two signals, as shown in FIG. 1.
Further, a cable 1 has a structure in which two twisted pairs (signal conductors) 3 shielded by a first shield layer 2 around its cross-section and a power wire 4 are bundled together and entirely shielded by a second shield layer 5, as shown in FIG. 2.
In the IEEE 1394 standards, there are provided two connection methods, namely, daisy chain and node branch. A daisy chain method is capable of connecting up to 16 hops of 1394 node, with the maximum distance between each node being 4.5 m. In the IEEE 1394 standards, up to 63 nodes can be connected by employing both methods of daisy chain and node branch in combination.
In the IEEE 1394 standards, the cable can be taken out or put in or the power turned on or off in the above connected state, while the other node is in operation. A 1394 topology is automatically reconstructed when a node is added or deleted. The ID or arrangement of the connected node is managed on the interface.
The components of the interface and the protocol architecture conforming to the IEEE 1394 standards are configured as shown in FIG. 3. Herein, the interface of the IEEE 1394 standards can be divided into three sections of hardware, firmware and software.
The hardware comprises a physical layer (PHY layer) and a link layer. In the physical layer, the signal of the IEEE 1394 standards is directly driven. The link layer has a host interface and an interface with the physical layer.
The firmware comprises a transaction layer consisting of a management driver for performing actual operations for the interface conforming to the IEEE 1394 standards, and a management layer consisting of a management driver conforming to the IEEE 1394 standards called a serial bus management (SBM).
The software is mainly an application layer, comprising a program employed by the user and a management program for providing the interface with the transaction layer or management layer.
In the IEEE 1394 standards, the transfer operation that occurs within a network is called a sub-action. For this sub-action, there are defined two transfer modes: an asynchronous transfer mode called asynchronous and a synchronous transfer mode called isochronous in which the transfer band is assured. Further, each sub-action can take any of three transfer states that are referred to as arbitration, packet transmission and acknowledgement. In the isochronous mode, the acknowledgement is omitted.
In an asynchronous sub-action, asynchronous transfer is made. FIG. 4 shows the transition state over time in this transfer mode. A first sub-action gap indicates an idle state of the bus. The termination of prior transfer can be detected by monitoring the time of this sub-action gap, and it is determined whether or not a new transfer is permitted. Herein, if the idle state continues for a certain time or more, the nodes C and D desiring the transfer determine that the bus is available, and send a request for the control right of the bus to a parent node, as shown in FIGS. 5A and 5B.
The parent node B that has accepted the transfer request from node C sends a data prefix for rejecting the control right of the bus to the ports other than the port having accepted the request, and repeats the request for the parent node A of its own. The root node A sends a grant for permitting the control right of the bus for the request accepted firstly and sends the data prefix to other ports.
All the nodes that have accepted the data prefix withdraw the request, and are placed in a data waiting state. One node can get the control right of the bus at any time by determining the control right of the bus in accordance with this procedure, thereby avoiding collision of the data.
The node that has acquired the control right of the bus in this arbitration executes the data transfer, or the packet transmission, following the data prefix. A target node that has received the transferred data responds by executing the acknowledgment of sending back ACK (reception acknowledge return code) in accordance with the received result.
By executing this acknowledgment, the transmission and reception nodes can confirm whether or not the data transfer has been performed normally, and may perform the retransmission of data in some cases. Afterwards, the nodes return to the sub-action gap or the idle state of the bus to repeat the above transfer operation.
In an isochronous sub-action, the data transfer is made fundamentally according to the same procedure as in the asynchronous sub-action, but preferentially is performed prior to the asynchronous transfer with the asynchronous sub-action. A packet for the isochronous transfer is shown in FIG. 18. The isochronous transfer in this isochronous sub-action is effected following a cycle start packet issued from the root node at about every 8 kHz. Thereby the node is placed in the transfer mode in which the transfer band is assured to implement the transfer of data in real time.
In the case where the isochronous transfer of real time data is performed among a plurality of nodes at the same time, the required real time data is received only by setting a channel ID for distinguishing the data in its transfer data.
FIG. 7 is a diagram showing the transmission cycle structure in which the asynchronous transfer with the asynchronous sub-action and the synchronous transfer with the isochronous transmission are mixed. In the IEEE 1394, the data is divided into packets and transmitted in time division with reference to a cycle having a length of 125 μS. This cycle is produced by a cycle start signal supplied from a node (any device connected to the bus) having a cycle master function. The isochronous packet secures a band (in unit of time but called a band) required for transmission from the beginning of all the cycles. Therefore, in isochronous transmission, the transmission of data within a fixed time is assured. If a transmission error occurs, the data is lost because there is no protection scheme. In asynchronous transmission in which a node having gotten the bus as a result of arbitration sends out an asynchronous packet within the time of each cycle not used for isochronous transmission, secure transmission can be assured by employing the acknowledge and retry, but the transmission timing is not fixed.
In order for a predetermined node to effect isochronous transmission, it is required that that node can cope with the isochronous function. At least one of the nodes coping with the isochronous function must have a cycle master function. Further, at least one of the nodes connected to the IEEE 1394 serial bus must have an isochronous resource manager function.
The IEEE 1394 conforms to a control & status register (CSR) architecture having an address space of 64 bits as defined in the ISO/IEC 13213. FIG. 8 is a diagram for explaining the structure of the address space in the CSR architecture. The first 16 bits indicate a node ID designating the node on the IEEE 1394, and the remaining 48 bits are employed to designate the address space given to each node. The first 16 bits are further divided into 10 bits of bus ID and 6 bits of physical ID (node ID in a narrow sense). Since the value in which all bits are one is used for a special purpose, 1023 buses and 63 nodes can be designated.
A space defined by the first 20 bits in the address space of 256 terabytes defined by the remaining 48 bits is divided into an Initial Register Space, a Private Space and an Initial Memory Space which are used for the registers specific to the CSR or specific to the IEEE 1394 of 2048 bytes. In the case where the space defined by these first 20 bits is the Initial Register Space, the space defined by the remaining 28 bits is divided into a Configuration Read Only Memory, an Initial Unit Space used for purposes specific to the node, and a Plug Control Register (PCRs).
FIG. 9 is a table listing the offset address, name and operation of the main CSRs. In FIG. 9, an offset indicates the offset address from FFFFF0000000h (the last number with h indicates the hexadecimal notation) at which the Initial Register Space begins. A Bandwidth Available Register having an offset of 220h indicates a band that can be allocated to isochronous communication, the value of the node operating as the isochronous resource manager being only validated. The CSR of FIG. 8 has each node, but the Bandwidth Available Register is validated only for the isochronous resource manager. In other words, only the isochronous resource manager substantially has a Bandwidth Available Register. The Bandwidth Available Register saves the maximum value when no band is assigned for isochronous communication, the value being decreased every time the band is assigned.
A Channel Available Register with an offset from 224h to 228h has each bit corresponding to a channel number from 0 to 63. When the bit is zero, it indicates that the channel is already allocated. The Channel Available Register of only the node operating as the isochronous resource manager is effective.
Turning back to FIG. 8, the configuration ROM based on a general read only memory (ROM) format is arranged at the addresses from 200h to 400h in the Initial Register Space. FIG. 10 is a diagram showing the general ROM format. The node in unit of access on the IEEE 1394 can have a plurality of units operating independently while sharing the address space in the node. The unit directories can indicate the version or location of software for these units. Though a bus info block and a root directory are at fixed locations, other blocks are at the locations specified by the offset address.
FIG. 11 is a diagram showing the details of the bus info block, the root directory and the unit directory. Company ID within the bus info block stores the ID number indicating the manufacturer of the device. Chip ID stores an ID specific to the device and unique in the world without duplication with the Ids of other devices. Also, in accordance with the IEC 61833 standards, a unit spec ID in the unit directory of the device satisfying the IEC 61883 standards is written as 00h in the first octet, A0h in the second octet, and 2Bh in the third octet. Moreover, a unit switch version is written as 01h in the first octet, and 1 at the least significant bit (ISB) in the third octet.
In order to control the input/output of the device via the interface, the node has a plug control register (PCR), as defined in the IEC 61883, in the addresses from 900h to 9FFh within the Initial Unit Space of FIG. 8. This substantiates a concept of plug to form a signal path logically analogous to the analog interface. FIG. 12 is a diagram showing the configuration of the PCR. The PCR has an output plug control register (oPCR) indicating the output plug and an iPCR (input Plug Control Register) indicating the input plug. Also, the PCR has an output master plug register (oMPR) and an input master plug register (iMPR) indicating the information of the output plug or input plug specific to each device. Each device does not have plural oMPRS and iMPRS, but can have plural oPCRS and iPCRS corresponding to individual plugs in accordance with the capability of the device. The PCR as shown in FIG. 12 has 31 oPCRs and iPCRs. The flow of isochronous data is controlled by manipulating the registers corresponding to these plugs.
FIGS. 13A to 13D are diagrams showing the configuration of an oMPR, oPCR, iMPR and iPCR. FIG. 13A shows the configuration of an oMPR, FIG. 13B shows the configuration of an oPCR, FIG. 13C shows the configuration of an iMPR, and FIG. 13D shows the configuration of an iPCR. A data rate capability of 2 bits on the MSB side of the oMPR and the iMPR stores a code indicating the maximum transmission rate of isochronous data that the device can transmit or receive. A broadcast channel base of the oMPR specifies the number of channels used for the broadcast output.
A number of output plugs of 5 bits on the LSB side of the oMPR stores the number of output plugs or the number of oPCRs provided for the device. A number of input plugs of 5 bits on the LSB side of the iMPR stores the number of input plugs or the number of iPCRs provided for the device. A non-persistent extension field and a persistent extension field are areas reserved for future extension.
An on-line field of MSB for the oPCR and the iPCR indicates the use status of the plug. That is, if this value is 1, the plug is ON-LINE, and if this value is 0, the plug is OFF-LINE. The value of a broadcast connection counter for the oPCR and the iPCR denotes the presence (1) or absence (0) of a broadcast connection. The value of a point-to-point connection counter having a width of 6 bits for the oPCR and the iPCR denotes the number of point-to-point connections provided for the plug.
The value of a channel number having a width of 6 bits for the oPCR and the iPCR denotes the number of isochronous channels to which the plug is connected. The value of a data rate having a width of 2 bits for the PCR denotes the actual transmission rate of packets of isochronous data output from the plug. The code stored in an overhead ID having a width of 4 bits for the oPCR denotes the bandwidth of overhead in the isochronous communication. The value of a payload having a width of 10 bits for the PCR denotes the maximum value of data contained in an isochronous packet that the plug can handle.
FIG. 14 is a diagram showing the relation between plug control registers and isochronous channels. The AV-devices 71 to 73 are connected via an IEEE 1394 serial bus. Of oPCR[0] to oPCR[2] for which the transmission rate and the number of oPCRs are specified by the oMPR of an AV device 73, isochronous data having the channel specified by oPCR[1] is forwarded to the channel #1 of the IEEE 1394 serial bus. Of iPCR[0] and iPCR[1] for which the transmission rate and the number of iPCRs are specified by the iMPR of an AV device 71, the AV device 71 reads the isochronous data forwarded to the input channel #1 of the IEEE 1394 serial bus, the input channel designated by iPCR[0]. Similarly, an AV device 72 forwards isochronous data to the channel #2 designated by oPCR[0] and the AV device 71 reads the isochronous data from the channel #2 designated by iPRC[1].
In this way, data transmission is made between the devices connected via the IEEE 1394 serial bus. In this system, each device can be controlled or judged for the status, employing an AV/C command set that is defined as the commands for controlling the devices connected via the IEEE 1394 serial bus. This AV/C command set will be described below.
Referring now to FIGS. 15 to 19, the data structure of the Subunit Identifier Descriptor in the AV/C command set for use with this system will be described first. FIG. 15 shows the data structure of the Subunit Identifier Descriptor. As shown in FIG. 15, this data structure is formed by a list of hierarchical structure of the Subunit Identifier Descriptor. The list represents the channels that can be received by a tuner, or the music recorded on a disk, for example. The uppermost level list in the hierarchical structure is referred to as a root list, and a list 0 is the root list for the lower level lists, for example. The lists 2 to (n−1) become likewise the root list. The root lists exist by the number of objects. Herein, an object is each channel in the digital broadcast when the AV device is a tuner, for example. All the lists in one hierarchy share the common information.
FIG. 16 shows the format of The General Subunit Identifier Descriptor for use with the existing system. In the Subunit Identifier Descriptor, the attribute information regarding the function is described in the contents. The value of a descriptor length field itself is not contained. A generation ID indicates the version of the AV/C command set, its value being “00h” (h indicates hexadecimal) at present, as shown in FIG. 8. Herein, “00h” means that the data structure and the command are at the version 3.0 of the AV/C General Specification. As shown in FIG. 17, all the values except for “00h” are reserved for future specification.
A size of list ID denotes the number of bytes for the list ID. A size of object ID denotes the number of bytes for the object ID. A size of object position denotes the location (number of bytes) in the list for use to be referenced in the control. A number of root object lists denotes the number of root object lists. A root object list id indicates the ID for identifying the root object list at the uppermost level in the independent hierarchy.
A subunit dependent length denotes the number of bytes in the subsequent subunit dependent information field. The subunit dependent information field stores information specific to the function. The manufacturer dependent length denotes the number of bytes in the subsequent manufacturer dependent information field. The manufacturer dependent information field indicates the specification information of the vendor (maker). In the case where there is no manufacturer dependent information in the descriptor, this field does not exist.
FIG. 18 shows the assignment ranges of the list ID as shown in FIG. 16. The areas of “0000h to 0FFFh” and “4000h to FFFFh” are reserved as the assignment range for future specification. The areas of “1000h to 3FFFh” and “10000h to max list ID value” are prepared to identify the dependent information of the subunit type.
The AV/C command set for use with this system will be described below.
FIG. 19 is a view for explaining the command and response of FCP in the AV/C command set. The FCP is a protocol for controlling the AV devices on the IEEE 1394 bus. As shown in FIG. 19, the controlling side is a controller, and the controlled side is a target. The transmission or response of FCP commands is made between the nodes, employing a write transaction of the asynchronous communication on the IEEE 1394 bus. The target having received the data sends back the acknowledge to the controller to acknowledge reception.
FIG. 20 is a diagram for explaining in more detail the relation between the command and response of FCP as shown in FIG. 19. A node A and a node B are connected via the IEEE 1394 bus. The node A is a controller and the node B is a target. The node A and the node B have a command register and a response register each of which is 512 bytes. As shown in FIG. 20, the controller writes a command message in the command register 93 of the target to pass an instruction. The target writes a response message in the response register 92 of the controller to pass a response. For the above two messages, the control information is transmitted and received. The sorts of command sets transmitted with the FCP are described in the CTS in the data field of FIG. 21, as will be described later.
FIG. 21 shows the data structure of packets transmitted in an asynchronous transfer mode of the AV/C command. The AV/C command set is for controlling the AV devices, with CTS (command set ID)=“0000”. An AV/C command frame and a response frame are transmitted and received between the nodes using the above-described FCP. The response to the command must be effected within 100 ms not to have a burden on the bus and the AV device. As shown in FIG. 21, the asynchronous packet data is composed of 32 bits (=1 quadlet) in the horizontal direction. The upper stage in the figure indicates a header part of the packet, and the lower stage indicates a data block. A destination_ID denotes the destination.
The CTS indicates the command set ID, with CTS=“0000” in the AV/C command set. A ctype/response field denotes the functional classification of the command when the packet is the command, or the processed result of the command when the packet is the response. For the commands, four classes are defined: (1) command (CONTROL) for controlling the function from the outside, (2) command (STATUS) for inquiring as to the status from the outside, (3) command (GENERAL INQUIRY (opcode supported or not) and SPECIFIC INQUIRY (opcode and operands supported or not)) for inquiring as to the support of control command from the outside, and (4) command (NOTIFY) for notifying the change of status to the outside.
The response is sent back in accordance with the sort of command. The responses for the CONTROL command include NOT IMPLEMENTED, ACCEPTED, REJECTED and INTERIM. The responses for the STATUS command include NOT IMPLEMENTED, REJECTED, IN TRANSITION and STABLE. The responses for the GENERAL INQUIRY and SPECIFIC INQUIRY commands include IMPLEMENTED and NOT IMPLEMENTED. The responses for the NOTIFY command include NOT IMPLEMENTED, REJECTED, INTERIM and CHANGED.
A subunit type is provided to specify the function within the device, for example, to assign tape recorder/player, tuner and so on. In order to discriminate the cases where there are plural subunits of the same type, the subunit id as the discrimination number is used for addressing. An opcode indicates the command and an operand indicates the parameter of the command. An Additional operand field as well as a padding are provided if necessary. A data CRC (Cyclic Redundancy Check) is employed for error check in the data transmission.
FIG. 22 shows a specific example of the AV/C command. FIG. 22A shows a specific example of a ctype/response. The upper stage in the figure denotes the command, and the lower stage denotes the response. “0000” is assigned to CONTROL; “0001” is assigned to STATUS; “0010” is assigned to SPECIFIC INQUIRY; “0011” is assigned to NOTIFY; and “0100” is assigned to GENERAL INQUIRY. The area from “0101 to 0111” is reserved for future specification. “1000” is assigned to NOT IMPLEMENTED; “1001” is assigned to ACCEPTED; “1010” is assigned to REJECTED; “1011” is assigned to IN TRANSITION; “1100” is assigned to IMPLEMENTED/STABLE; “1101” is assigned to CHANGED; and “1111” is assigned to INTERIM. “1110” is reserved for future specification.
FIG. 22B shows a specific example of a subunit type. “00000” is assigned to Video Monitor; “00011” is assigned to Disk recorder/Player; “00100” is assigned to Tape recorder/Player; “00101” is assigned to Tuner; “00111” is assigned to Video Camera; “11100” is assigned to Vendor unique; and “11110” is assigned to Subunit type extended to next byte. “11111” is assigned to unit, which is employed when the AV/C command is transmitted to the device itself, for example, the power source being turned on or off.
FIG. 22C shows a specific example of an opcode. An opcode table exists for each subunit type, and an opcode is shown in a case where the subunit type is Tape recorder/Player. Also, an operand is defined for each opcode. Herein, “00h” is assigned to VENDOR-DEPENDENT; “50h” is assigned to SEARCH MODE; “51h” is assigned to TIMECODE; “52h” is assigned to ATN; “60h” is assigned to OPEN MIC; “61h” is assigned to READ MIC; “62h” is assigned to WRITE MIC; “C1h” is assigned to LOAD MEDIUM; “C2h” is assigned to RECORD; “C3h” is assigned to PLAY; and “C4h” is assigned to WIND.
FIG. 23 shows a specific example of the AV/C command and the response. For example, when a reproduction or play instruction is issued to the reproducing device as the target (consumer), the controller sends a command to the target, as shown in FIG. 23A. Since this command uses the AV/C command set, CTS=“0000”. ctype=“0000” because a command (CONTROL) for controlling the device from the outside is employed (see FIG. 22A). Since subunit type is Tape recorder/Player, subunit type=“00100” (see FIG. 22B). Since id is ID0, id=000. opcode=“C3h”, which means PLAY (see FIG. 22C). operand is “75h” meaning FORWARD. If reproduced, the target sends back a response to the controller as shown in FIG. 23B. Herein, response=“1001” meaning ACCEPTED (see FIG. 22A). Other items are the same as in FIG. 23A, except for response, and not described here.
The physical layer in the IEEE 1394 standards has a physical layer logical block (PHY Logic) 11, a selector block (RXLOCK/DATASELECTOR) 12, port logical blocks (PORT LOGIC1, PORT LOGIC2, PORT LOGIC3) 13, 14 and 15, cable ports (CABLE PORT1, CABLE PORT2, CABLE PORT3) 16, 17 and 18, and a clock generation block (PLL) 19, as shown in FIG. 24.
In this example, though the functions have been thus described using a physical layer having three ports, these functions do not depend on the number of ports.
The physical layer logical block 11 performs the I/O control and the arbitration control with the link layer in the IEEE 1394 standards, and is connected to a link layer controller (LINK CONTROLLER) 10, as well as the selector block 12 and the port logical blocks 13, 14 and 15.
The selector block 12 selects the data DATA1, DATA2 and DATA3 received via the port logical blocks 13, 14 and 15 connected to the cable ports 16, 17 and 18, and the reception clocks RXCLK1, RXCLK2 and RXCLK3, and is connected to the physical layer logical block 11 and the port logical blocks 13, 14 and 15.
In the case of data transfer, this selector block 12 transfers the packet data passed from the physical layer logical block 11 to all the port logical blocks 13, 14 and 15. Also, in the case of reception, the selector block 12 selects one pair among the packet data DATA1, DATA2 and DATA3 received via the port logical blocks 13, 14 and 15 and the reception clocks RXCLK1, RXCLK2 and RXCLK3, and sends the packet data DATA1 and its reception clock RXCLK1 received via the cable port 16 by the port logical block 13, for example, to the physical layer logical block 11.
The packet data selected by the selector block 12, for example, the packet data DATA1 received by the port logical block 13, is written into an FIFO memory within the physical layer logical block 11 at its reception clock RXCLK1. The packet data written into this FIFO memory is read at a system clock SYSCLK given by the clock generation block 19.
The port logical block 13 transmits or receives the arbitration signal ARB1 and the data DATA1 via the cable port 16 and has a function of generating a reception clock RXCLK1 from the data and its strobe signal sent via the cable port 16. Also, this port logical block 13 has the arbitration signal ARB1 passed from the physical layer logical block 11 at the time of arbitration. And at the time of receiving the data, the port logical block 13 sends the packet data DATA1 received via the cable port 16, together with its reception clock RXCLK1, via the selector block 12 to the physical layer logical block 11.
And, in the case where this port logical block 13 is selected by the selector block 12, the packet data DATA1 is written into the FIFO memory within the physical layer logical block 11 at its reception clock RXCLK1.
The port logical block 14 transmits or receives an arbitration signal ARB2 and the data DATA2 via the cable port 17 and has a function of generating a reception clock RXCLK2 from the data and its strobe signal sent via the cable port 17. Also, this port logical block 14 has the arbitration signal ARB2 passed from the physical layer logical block 11 at the time of arbitration.
And, at the time of receiving the data, the port logical block 14 sends the packet data DATA2 received via the cable port 17, together with its reception clock RXCLK2, via the selector block 12 to the physical layer logical block 11. In the case where this port logical block 14 is selected by the selector block 12, the packet data DATA2 is written into the FIFO memory within the physical layer logical block 11 at its reception clock RXCLK2.
The port logical block 15 transmits or receives an arbitration signal ARB3 and the data DATA3 via the cable port 18 and has a function of generating a reception clock RXCLK3 from the data and its strobe signal sent via the cable port 18. Also, this port logical block 15 has the arbitration signal ARB3 passed from the physical layer logical block 11 at the time of arbitration. And at the time of receiving the data, the port logical blocks 15 sends the packet data DATA3 received via the cable port 18, together with its reception clock RXCLK3, via the selector block 12 to the physical layer logical block 11.
In the case where this port logical block 15 is selected by the selector block 12, the packet data DATA3 is written into the FIFO memory within the physical layer logical block 11 at its reception clock RXCLK3.
The cable port 16 drives the twisted pair cable by a signal sent from the port logical block 13, and level-converts and sends a signal passed via the twisted pair cable to the port logical block 13. The cable port 17 drives the twisted pair cable by a signal sent from the port logical block 14, and level-converts and sends a signal passed via the twisted pair cable to the port logical block 14. The cable port 18 drives the twisted pair cable by a signal sent from the port logical block 15, and level-converts and sends a signal passed via the twisted pair cable to the port logical block 15.
The clock generation block 19 generates a system clock SYSCLK of 49.152 MHz and a transmission clock of 98.304 MHz (S100) from the clock of 24.576 MHz supplied from a crystal oscillator (X′TAL) 20.
The logical value of the arbitration signal in the physical layer is any one of three values “0”, “1” and “Z”, produced in accordance with the rules shown in FIGS. 25 and 26, and decoded in accordance with the rules shown in FIG. 27. The value “Z” indicates a passive state of driver.
Herein, of two twisted pairs, one twisted pair TPA/TPA* passes a strobe signal (Strb_Tx), and accepts a data signal (Data_Rx). On the other hand, another twisted pair TPA/TPA* passes a data signal (Data_Tx) and accepts a strobe signal (Strb_Rx). The signals Strb_Tx, Data_Tx, Strb_Enable and Data_Enable are used to generate the arbitration signals (Arb_A_Rx, Arb_B_Rx).
In the physical layer, two transmission arbitration signals Arb_A_Tx and Arb_B_Tx are encoded into the line status in accordance with the rules as shown in FIG. 28. The line status has a different meaning, depending on whether the signal is sent to the parent node or the child node, as shown in FIG. 28.
Herein, the relation between parent and child in the IEEE 1394 standards will be described below. Of a plurality of nodes connected in accordance with the IEEE 1394 standards, some nodes are located at a leaf (end). Immediately after the bus reset, each node determines whether or not it is located at a leaf. A determination of whether or not each node is at a leaf can be effected by recognizing how many cables are connected to itself.
That is, a node having only one port or a plurality of ports but with only one cable connected becomes a leaf. Each leaf makes an inquiry to the parent node to be connected. The parent node accepting the inquiry that the node connected to the port from which the inquiry originates is made a child node and further makes an inquiry to the connection destination from the port having the parent-child relation undecided. In this way, the parent-child relation within the bus is decided. Ultimately, the node that is parent for all the ports of its own becomes the root. Also, in the physical layer, the interpolation arbitration signals Arb_A_Tx and Arb_B_Tx are decoded into the line status in accordance with the rules shown in FIG. 29.
In the IEEE 1394 standards, there are required conditions for the interface connecting a home appliance handling video data to a computer, enabling a home network to be constructed by connecting through one cable a variety of devices including an audio device, a visual device and a personal computer in the general home, whereby the variety of devices can be simply operated.
However, in the IEEE 1394 standards, because the distance between devices to be connected or the internodal cable length is defined to be 4.5 m at maximum, several nodes must be provided only for the junction of cables, if a network over a plurality of rooms in a home is constructed.
If the cable length is extended without changing the physical layer method in the IEEE 1394 standards, the cable must be thicker, resulting in not only reduced workability for leading the cable for the network, but also expensive cables.
In order to avoid such a problem, a digital serial interface device (LD1394: Long Distance IEEE1394) has been proposed in which a digital serial data interface has an extension of internodal cable to make arbitration for the control right of the bus prior to the data transfer to effect long distance as in the IEEE 1394 standards.
By the way, in the LD 1394, it typically takes more time to make negotiation, owing to an increased cable delay caused by the long distance, than in the IEEE 1394 standards. Hence, there is a problem that the band usable for the data transfer is limited. Therefore, an attempt to make effective use of the band by optimizing the gap count in the topology containing the LD 1394 is considered to be important.
However, in the IEEE 1394 standards, it is specified that the PHY packet must be transferred at a rate of S100, and in the p1394a that is an extended specification of the IEEE 1394 standards, a ping packet defined as one of the PHY packets must be transferred at a rate of S100 at any time. Accordingly, the internodal propagation time that is obtained employing the ping packet is the propagation time between nodes when the data is transferred at a transfer rate of S100.
However, in the IEEE 1394 standards, because the topology of devices can be constructed relatively freely, it is sufficiently considered that the topology may contain in its path the physical layer with a different PHY delay in repeating the data depending on the transfer rate of data as seen in the physical layer of the LD 1394.
In such a topology, considering the case that the data flowing through the topology is always at a higher transfer rate than S100, the internodal propagation time, measured employing the ping packet transferred at a rate of S100, is greater than the propagation time taken for the actual data transfer. Therefore, the gap count calculated on the basis of the internodal propagation time is increased, resulting in a problem that the gap count can not be appropriately optimized.